COMPUTER ORGANIZATION

(Machine Instructions, Addressing Models, ALU & Data Path)

PRACTICE SET 1

Table of Contents

1 Practice Questions in Computer Architecture and Organization for Gate Exam
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Practice Questions in Computer Architecture and Organization for Gate Exam

1. Which of following may not definitely occur in an instruction cycle?

(i) Fetch cycle (ii) Execution cycle

(iii) Indirect cycle

(a) (i) only (b) (i) and (ii)

2. Most relevant addressing mode to write position independent code is

(a) Direct (b) Indirect

3. Which set of instruction transfers the memory word specified by the effective address to AC or Load to AC?

(a) DR←M[AR]AC←AC+DR,E←COUT,SC←O (b) DR←M[AR]AC←DR,SC←O

4. A certain machine uses expanding opcode. It has 16-bit instructions and 6-bit addresses. It supports one address and two address instructions only. If there are ‘n’ two address instructions, the maximum number of one address instruction is

(a) 2¹⁶– n (b) 2¹⁰ – n

^{(c) (24 – n) × 26 (d) 210}

5. Booth’s algorithm is used in floating point

(a) Addition (b) Subtraction

6. Consider the following format of 32 bit floating point number:

Sign: 1 bit

Exponent: 8 bits

Mantissa: 23 bits

The mantissa is normalized and has an implied “1” on the left of the point. Normalized form of mantissa is 1.MMMMM………

The exponent is formatted using excess-127 notation, with an implied base of 2

What will be the decimal value of the following 32 floating point number stored in above mentioned format?

1 10000010 11110110000000000000000

(a) – 15.6875 (b) – 19.8976

7. For a carry look ahead adder, the general formula for gi and pi are

gi=ai∙bi , Pi=ai+bi where gi is the ‘generate’ part and pi is the ‘propagate’ part

Assume you are adding two 4 – bit numbers a3a2a1a0+b3b2b1b0

and c0 is the carry-in to the least significant bit (LSB) (normally, a ripple-carry adder has no carry-in to the LSB, but pretend you have a full adder adding the LSB).

Write a formula for c2 for a carry look ahead adder.

(a) (a1b1)+((a0b0)(a1+b1)+(a1+b1)(a0+b0)c0) (b) (a1b1)+(a1b1)(a0+b0)+(a1+b1)(a0+b0)c0 (c) (a1b1)+(a0b0)(a1+b1)c0+(a1+b1)(a0+b0)c1 (d) (a1b1)+(a0b0)(a1+b1)+(a1+b1)(a0+b0)

8. Consider the following floating –point format:

Mantissa is in fraction in sign magnitude form.

What will be the value of mantissa in hexadecimal for number 56.75?

(a) D3 (b) E3

9. In the figure, A is a parallel – in, parallel – out 4 bit register which loads at the rising edge of the clock C. The input lines are connected to a 4 bit bus W. Its output acts as the input to a 16 × 4 ROM whose output is floating when the enable input E is a 0. A partial table of the contents of the ROM is as follows:

The clock to the register is shown and the data on the W bus at time t1 is 0110. The data on the bus at time t2 is 10.

In the adder circuit shown below, X=X2X1X0,Y=Y2Y1Y0 are the inputs, and S=S3S2S1S0 is the output. M and C are control input lines, and FA refers to a full adder.

In this problem + represents binary addition, and – represents binary subtraction in either one’s or two’s complement form.

The logic expressions describing a full adder are (a) Si=Xi⊕Yi⊕Ci,Ci+1=Ci∪XiYi (b) Si=Xi⊕Yi⊕Ci,Ci+1=(Xi⊕Yi)Ci∪XiYi (c) Si=Xi⊕Yi⊕Ci,Ci+1=Ci∩XiYi (d) Si=Xi⊕Yi⊕Ci,Ci+1=Ci(Xi∪Yi )

11. Match List-I with List-II and select the correct answer using the codes given below the lists:

List-I List-II

A. Pointer 1. Indirect addressing mode

B. Position independent code 2. Immediate addressing mode

C. Constant operand 3. Relative addressing mode

Codes:

A B C

(a) 1 2 3 (b) 3 2 1 (c) 1 3 2 (d) 2 3 1

12. Consider the following sequence of micro-operations.

MBR ‹ PC

MAR ‹ SP

M[MAR] ‹ MBR

PC ‹ Vector address.

Which of the following operation performed by this sequence?

(a) Instruction fetch (b) Operand fetch

Q13.In which of the following addressing mode, the content of the program counter is added to the address part of the instruction to get the effective address?

(a) Indexed addressing mode (b) Implied addressing mode

14. Consider the following program segment:

Instruction Meaning Size (words)

I1 LOAD r0, 500 r0 ⃪ [500] 2

I2 MOV r1, r0 r1 ⃪ [r0] 1

I3 ADD ro, r1 r0 ⃪ r0 + r1 1

I4 INC r0 r0 ⃪ r0 + 1 1

I5 INC r1 r1 ⃪ r1 + 1 1

I6 ADD r0, r1 r0 ⃪ r0 + r1 1

I7 Store r1, r0 M[(r1)] ⃪ r0 2

I8 Halt Stop 1

Assume that memory is word addressable with word size 32 bits. Program is loaded into memory location (3000)10 onwards. The value of PC at the end of execution of above program is __________

15.Which of the following requires a device driver ?

(A) Register (B) Cache

16.Which of the following is not a form of memory ?

(A) Instruction cache (B) Instruction register

17.Horizontal microprogramming

(A) Does not require use of signal decoders

(B) Results in larger sized microinstructions than vertical

microprogramming

(D) All of the above

18.Which of the following addressing modes are suitable for program relocation at run time?

1. Absolute addressing 2. Based addressingm3. Relative addressingmm4. Indirect addressing

(A) 1 and 4 (B) 1 and 2

19.Consider a multiplexer with X and Y as data inputs and Z as control input.Z = 0 selects input X , and Z =1 selects input Y . What are the connection required to realize the 2-variable Boolean function

f TR = + , without using any additional hardware?

(A) R to X, 1 to Y, T to Z (B) T to X, R to Y, T to Z

20.Consider the following program segment for a hypothetical CPU

having three user registers R1,R2 and R3.

Consider that the memory is byte addressable with size 32 bits, andmthe program has been loaded starting from memory location 1000m(decimal). If an interrupt occurs while the CPU has been halted after executing the HALT instruction, the return address (in decimal)msaved in the stack will be

(A) 1007 (B) 1020

21.Let the clock cycles required for various operations be as follows:

Register to/from memory transfer: 3 clock cycles

ADD with both operands in register: 1 clock cycle

Instruction fetch and decode: 2 clock cycles per word

The total number of clock cycles required to execute the program is

(A) 29 (B) 24

22.The microinstructions stored in the control memory of a processor have a width of 26 bits. Each microinstruction is divided into three fields: a micro-operation field of 13 bits, a next address field (X), anda MUX select field (Y). There are 8 status bits in the inputs of the

MUX .How many bits are there in the X and Y fields, and what is the size of the control memory in number of words?

(A) 10, 3, 1024 (B) 8, 5, 256

23.The instruction “call Rn, sub” is a two word instruction. Assuming

that PC is incremented during the fetch cycle of the first word of the

instruction, its register transfer interpretation is

Rn PC <= = 1;

PC <= M [PC ]

The minimum number of CPU clock cycles needed during the

execution cycle of this instruction is

(A) 2 (B) 3