Computer organization mcq for GATE
This computer organization mcq based tutorial provides some practice questions for GATE CS/IT Exam.Computer organization and architecture is an important subject for GATE CSE Exam.
It consist of approx 8-10 marks questions every year in GATE Exam. Here in this tutorial we discussed some computer organization mcq for GATE EXAM practice from different topics of this subjects.
Questions and Answers
These computer organization mcq are generally based on the following concepts of the computer organization and architecture subject. Computer science graduate should know the answers of following questions and concepts in order to solve these computer organization gate questions.
- What is logical address and physical address?
- What is page and frame ?
- what are zero address, one address, two address and thress address formats of an instruction?
- What do you understand by Interrupt?
- What is microinstruction ?
- What is the difference between horizontal and vertical micro instructions?
- how to compute 2’s complement of a binary number ?
Computer Organization MCQs
Here are some computer organization mcq for GATE Exam Practice.
Q1. Consider a logical address space of 8 pages of 512 words each mapped onto a physical memory of 64 frames. How many bits are there in physical address?
Solution: From 15.45 To 14.55
Q2. How many cycles are required for a 100 MHz processor to execute a program which requires 5 seconds of CPU time?
(a) 109 cycles (b) 50 × 107 cycles
(c) 108 cycles (d) 50 cycles
Solution: Option (b)
Explanation: Cycle time=109100×106=10 ns; Number of cycles=5×10910=50×107cycles
Q3. Arrange the following configurations for CPU in decreasing order of operating speeds.
1. Hard wired control
2. Vertical microprogramming
3. Horizontal microprogramming
(a) 1 > 2 > 3 (b) 1 > 3 > 2
(c) 2 > 3 > 1 (d) 3 > 2 > 1
Solution: Option (b)
Explanation:
Micro programmed control unit uses microinstructions, for generating control signals.
Q4. A = 1111 1010, B = 0000 1010 be two 8-bit 2’s complement numbers. Their product in 2’s complement is
(a) 1100 0100 (b) 1001 1100
(c) 1010 0101 (d) 1101 0101
Solution: Option (a)
Explanation: −6×10=−60
It can be represented in 2’s complement as 11000100
Q5. Main difference between CISC and RISC is
(a) RISC has few instructions (b) RISC has few addressing modes
(c) CISC is having fewer registers (d) Both (a) & (b)
Solution: Option (d)
Q6. A computer supports one address and two address instructions. All the Addresses are the memory addresses. Memory size is 1Mbyte. How many one address instructions are possible if it has 240 two addresses instructions? (Assume binary instructions code has 48 bits)
(a) 22016 (b) 16×220
(c) 228−256 (d) None of these
Solution: Option (b)
Explanation:
One Address = (256 – 240) × 220 = 16 × 220
Q7. An interrupt program takes one cycle for every instruction. A DMA takes 15 cycles for initialization and 2 cycles for each Byte to transfer; what is the speed up of DMA over interrupt program of 5 instructions for the transfer of 100 Bytes? (Interrupt program must be executed for every byte)
Solution: From 2.369 To 2.231
Explanation: DMA=15+100×2=215 Intrpt=(1×5)×100=500; Speed up=500215≈2.3
Q8. How many separate address and data lines are needed for a memory of 8K × 16?
(a) 13 address, 3 data lines (b) 13 address, 16 data lines
(c) 12 address, 4 data lines (d) 13 address, 4 data lines
Solution: Option (b)
Explanation: Memory size=8K×16=213×16. So,address line=13,data line=16
(24−4)×26=12×64=768
Q9. A system supports 1-address and 2-address instructions. If the instruction length is 16-bits and memory is having 64 words, how many 1-address instructions exists if there are ‘8’ 2-address instructions?
Solution: From 527.36 To 496.64
Explanation:
Total number of 1-address instructions is (24−8)∗26=512
Q10. What is the average memory access time for a 3 level memory system where T2 = 2T1 and T3 = 3T1 and hit ratios h1 = h2 = 0.9. [Ti is effective access time]
(a) 1.11T1 (b) 1.22T1
(c) 1.09T1 (d) 1.01T1
Solution: Option (a)
Explanation: 0.9[T1]+0.1[0.9[2T1]+0.1[3T1]]=1.11T1
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