Table of Contents
- 1 Computer Architecture Interview Questions
Computer Architecture Interview Questions
Computer Organization and Networking Architecture are important subjects of computer science and engineering branch. Questions from both computer organization and networking architecture are generally asked in technical interview for the post of hardware and networking architecture such as network administrator, system analyst.
Computer Organization and networking architecture Related questions are also asked in GATE (CS/IT) or UGC NET examination. Computer Science students are requested to Read these questions till the end.
In this Tutorial we Have discussed various Computer Organization and networking architecture questions in Three Section.
Short Type Networking Architecture Questions
Some short type computer organization and networking architecture questions are given below. Read These questions and Prepare for the computer network architect interview.
Q1. Perform ASHR, ASHL, LSHR, LSHL operation individually on binary data 11001011.
Q2. What is an instruction? Explain format of 3-Address Instruction.
Q3. What are instruction cycles and sub cycles.
Q4. Explain memory operation : R5←M [R5]
Q5. Specify control word for Micro-Operation: R7←R1.
Q6. Convert into post fix : A+B * [C*D+E* (F+G)]
Q7. Differentiate SRAM and DRAM.
Q8. Explain Bus arbitration with suitable diagram.
Q9. Explain different types of Bus with suitable diagram.
Q10. Write difference between Hardwire and micro programmed control.
Q11. Explain Stack Organization.
Q12. Explain Hard Disk structure.
Q13. Explain Memory Reference & Register Reference Instruction.
Q14. What do you understand by Array Multiplier?
Q15. Differentiate between Static Ram & Dynamic RAM.
Q16. Explain Hard Disk structure & working operation.
Q17. Explain different types of bus arbitration.
Q18. Define Microprogram Sequencer.
Q19. Explain Interrupt.
Q20. What is a control word?
Q21. Explain synchronous & asynchronous communication.
Q22. Write a short note on Indirect Addressing.
Q23. Write a short note on RISC ( Reduced Instruction Set Computer) .
Q24. What is microcode?
Q25. What is Programmed I/o?
Q26. What is the benefit of using multiple bus architecture compared to single bus architecture?
Q27. Explain FLYN and FENG’s classification.
Q28. Perform SHR, SHL, ASHR & ASHL operation individually on binary data 11001011.
Q29. Define Pipelining.
Q30. Explain 3 address format of an instruction with example.
Q31. Differentiate Microprogrammed control unit & Hardiwired control unit.
Q32. Define Stack.
Q33. Differentiate Horizontal & Vertical microprogramming.
Q34.Explain Double precision representation of floating point number.
Q35.Define Locality of Reference.
Q36. What are zero address instructions? Explain with the help of an example.
Q37.Convert the following decimal numbers to the bases indicated.
(i)7625 to octal (ii)1983 to Hexadecimal
(iii) 174.5 to Binary (iv) 3001 to Hexadecimal
Q38.Why do we need Virtual Memory?
Q39. Differentiate between synchronous and asynchronous communication.
Q40. Define hit ratio.
Q41. How many 128x8RAM chips are needed to provide a memory capacity of 2048 bytes.
Q42. What in general terms in the distinction between computer organization and computer architecture?
Q43. Define Pipelining.
Q44.Give the internal structure of a CPU.
Q45. Explain Cache Memory and it’s Performance Issues.
Computer Architecture Numerical Problem
Numerical problem in computer organization and computer networking architecture are discussed as follow-
Q1.Perform subtraction in given unsigned binary numbers- using 2’s complement-
- 10011 from 110001
- 110000 from 10101
Q2.Explain relative, indexed, indirect and register indirect addressing modes.
An instruction is stored at location 400 with its address field at 40 %. The address field has value 200. A processor register RI contains the number 600. Evaluate effective address if addressing mode of instruction is:-
- direct
- relative
- immediate
Note – To solve the above questions students have to understand the concept of addressing modes and it’s types.
Q3.Multiply 7 and -3 using booth algorithm. Use 4 bit representation.
Q4. Represent (0.0625)10 in single precision and double precision formats.
Q5. Show step by step the multiplication process using booth’s algorithm when (+15) and
(-13) numbers are multiplied. Assume 5-bit registers that gold signed numbers
Q6. Represent (1259.125)10 in single precision and double precision representation.
Q7. Multiply (+16)10 and (+31)10 using basic multiplication algorithm.
Q8. Multiply (+16)10 and (+31)10 using basic multiplication algorithm.
Q9. A 2 –way set associative cache can accommodate a total of 2048 words from the main memory. The main memory size is 128*32.
(i) Formulate all pertinent information required to construct the cache memory.
(ii) What is the size of the Cache Memory?
Q10. Explain address translation and paging concept in virtual memory with suitable diagram
| Page | Block |
| 0 | 3 |
| 1 | 1 |
| 4 | 2 |
| 6 | 0 |
Make a list of all virtual addresses (in decimal) that will cause a page fault if used by the CPU.
Q11. Multiply 7 and -3 using Booth Algorithm use 4-bit representation.
Q12. Explain micro-programmed control unit organization with suitable diagram.
Q13. Design an arithmetic circuit with one selection variable S & two n-bit data inputs A and B. the circuit generates the following four arithmetic operations in conjunction with the input carry cin. Draw the logic diagram for the first two satges:
Q14. Explain the various modes of data transfer. Write a short note on DMA.
Q15. If the size of logical address space is 256 KB & the size of main memory is 128 KB size of each page is 32 KB. Then find the following:
(i) How many bits are there in Logical address & physical address.
(ii) No. of Bits in Page No. & page offset field.
(iii) Total No. of frames in main memory.
Q16. Explain Associative and set-associative cache mapping techniques. A computer has a 4K word cache organized in block set associative manner, with 4 blocks way per set. the main memory contain 65536 Blocks. How many bits are there in each of TAG, Line block and index field of RAM & Cache Address. It is given that size of each Block is 64 words
Q17.A computer system has a 4 K word cache organized in block set associative manner with 4 blocks per set. 64 words per block. The main memory contains 65536 How many bits are there in each of TAG, SET and WORD fields?
Q18. At memory address 200 a two word instruction is loaded to AC with it mode bit as MSB. At location 201 the address stored is 500. At address 202 the next instruction is stored. A register R1 is use for Register addressing and the content R1 is 400. Then calculate the effective address using following addressing Mode.
i.Direct ii. Indirect iii. Index
iv. Relative v. Immediate
Q19. What do you understand by addressing mode? An instruction is stored at location 400 with its address hold at 401. The address field has value 200. A process register R1 contain the value 600. Calculate effective address using following addressing mode-
(i) Direct (ii) Relative (iii) Register Indirect
Computer Networking Architecture Program Questions
Q1. Consider the expression on:
y = (A-B) * (((C-D*E)/F)/G).
Write a program to evaluate the expression using one address instruction.
Q2.Write a program to evaluate the expression with 3 address, 2 address, 0 address instruction
Q3. Show stack operation and write program to solve the given expression
(3+4) [10(2+6)+8]
Long Explanation Computer Organization Questions
Long Questions asked form Computer Organization and Networking Architecture Subject are Given below
Q1.Explain different functional units and their interconnection with suitable diagram.
Q2.Discuss the types of bus in brief.
Q3. What do you understand by bus arbitration? Explain centralized and distributed bus arbitration.
Q4. Show the block diagram of the hardware that implements following register transfer statement: yT2 : R3←R1, R1←R3
Q5. Discuss advantages and disadvantages of Daisy chain method of bus arbitration.
Q6. Define data Bus, Address Bus and Control Bus.
Q7. Define computer Organization and RTL.
Q8. What do you understand by Bus Architecture? Explain with suitable diagram.
Q9. What do you mean by micro instruction? Explain micro programmed control unit organization with suitable diagram. Also write the difference between horizontal & vertical micro programming.
Q10. With the help of suitable table, design and explain the function of 1-6it ALU. Which performs all basic arithmetic & logic micro operations?
Q11. Explain the need of memory hierarchy in a computer system.
Q12. Explain execution of a complete instruction using a suitable example. Write control sequence steps also.
Q13. Explain 2 D & 2 ½ D memory organization.
Q14. Explain the concept of virtual memory with the help of necessary diagrams explain how address translation in performed in it.
Q15. What do you mean by asynchronous data transfer? Explain strobe controlled and handshaking mechanism for asynchronous data transfer.
Q16. Classify computers on the basis of Flynn’s architecture scheme.
Q17. What do you understand by address mode? Explain different types of address modes in detail with suitable example.
Q18. What are semiconductor RAM memories? Show the read operation & write operation in static memories with examples.
Q19. What is the purpose of DMA module? Discuss working of DMA.
Q20.Explain how processor responds to an interrupt with their types & exception.
Q21. What are various Branch handling mechanism in pipelined processer?
Q22. Explain differences between parallelism and pipelining by implementation point of view.
Q23.Explain Multiply (-8) and (3) using with 5-bit representation algorithm with flow chart.
Q24. Define the following term
(i) Microinstruction ii. Microoperation
iii. Control word iv. Register Transfer v. Memory Transfer.
Q25. Explain different types of Memory Reference and input output instruction
Q26. Explain different functional units and their interconnection with suitable diagram.
Q27. Explain general register organization in detail.
Q28.Explain Bus Arbitration process and it’s types.
Q29. Explain stack organization in detail.
Q30. Make flowchart of booth’s multiplication algorithm. Also multiply 2 and -4 using booth’s multiplication algorithm.
Q31. Define Data bus, Control bus and Address bus.
Q32. Explain bus architecture.
Q33. Explain addressing modes with examples in details.
Q34. Explain concept of virtual memory with the help of necessary diagram. Also explain the address translation from virtual address to physical address.
Q35. Explain the operation of three state bus buffers and show its using design of common bus.
Q36. What is the significance of addressing modes? Describe various addressing modes with suitable examples.
Q37. Draw the flowchart and explain the execution of a complete instruction in a basic computer.
Q38.What is the difference between spatial locality and temporal locality of reference? Explain 2D and 2.5D memory organization with suitable block diagrams.
Q39. Explain interrupts and its types write a short note on interrupt hardware.
Q40. Describe the performance metrics and measures used in computer system.
Q41. Discuss the need of fast adders. Explain carry look ahead adder with suitable diagram.
Q42. Explain flow chard for Booth Multiplication Algorithm with suitable example for multiplication of 4 and -2.
Q43.Discuss the basic concept of microprogram control and hardwired control unit. Describe any one method used for designing of hardwired control unit.
Q44.Evaluate the following expression:-
X=(A-B+C*(D*E-F))/(G+H*K) using three one and zero address instruction.
Q45. What is direct memory access? Explain with a suitable diagram. What is cycle stealing and burst transfer in DHA.
Q46. Explain serial communication and describe its types. Differentiate between serial and parallel communication.
Q47. Describe pipelining with suitable diagrams. Explain how pipeline performance can be measured.
Q48. Write a short note on optimization of cache performance.
Q49. Explain all the addressing modes in detail.
Q50. Explain stack organization in detail.
Q51. Discuss the concept of look ahead carries adder in detail.
Q52. Explain the concept of Booth’s algorithm for multiplication in detail with suitable example.
Q53. Explain various techniques for bus arbitration in detail.
Q54. Differentiate computer architecture and computer organization.
Q55. Explain various types of buses with its architecture.
Q56. Explain all the addressing modes in detail.
Q57. Explain stack organization in detail.
Q58. Discuss the concept of look ahead carries adder in detail.
Q59. Explain the concept of Booth’s algorithm for multiplication in detail with suitable example.
Q60. Explain various techniques for bus arbitration in detail.
Q61. Differentiate computer architecture and computer organization.
Q62. Explain various types of buses with its architecture.
Q63. What do you understand by microinstruction? Explain microprogramming control unit organization with suitable diagram in detail.
Q64. Explain the circuit for the designing of ALU in detail with suitable diagrams.
Q65. Explain the concept of Register organization in detail.
Q66. Multiply 7 and -3 using booth multiplication algorithm.
Q67. Explain instruction cycle and sub cycle with suitable diagram.
Q68. Explain Hardwired control unit design.
Q69. Explain various addressing modes in detail.
Q70. What is addressing mode? Explain the various types of addressing modes with example.
Q71. Discuss Hardwired Programmed control in detail.
Q72. Explain the concept of virtual memory in detail.
Q73. Explain DMA in detail.
Q74. Explain the concept of stack organization in detail.
Q75. Explain various techniques for Bus arbitration.
Q76. Design an Arithmetic and logical unit with proper diagrams
Q77. Explain 2D and memory organization.
Q78. Discuss different Cache Mapping Techniques.
Q79. Explain Micro-Program sequencer for control memory.
Q80. Explain the flow chart for instruction cycle.
Q81. Describe asynchronous data transfer. Explain strobe control and Handshaking method.
Q82. What do you mean by modes of transfer? Explain the following
(i) Programmed I/o (ii)Interrupt initiated I/o
Q83. Explain different types of Registers in a Computer System.
Special Practice Questions for GATE/UGC NET Exam
Students preparing for GATE(CS/IT) and UGC NET can practice the important problem solving computer architecture questions on our portal. The Link is Given Below –
Computer Organization GATE Questions
Conclusion and Summary
In this tutorial we have explained computer organization and architecture interview questions. These networking architecture and computer organization questions will be helpful for computer science students.
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