Q1. A program consists of four major types of instructions. The instruction mix and the CPI for each instruction type are given in the following table. If the clock frequency of the processor is 400 MHz, what is the average CPI of the processor?

(a) 3.75 (b) 2.87

(c) 1.87 (d) 1.54

Answer :

Option (c)

Explanation: Average CPI = Σ CiIi

= 1 × 0.5 + 2 × 0.23 + 3 × 0.17 + 4 × 0.1

= 0.50 × 0.46 + 0.51 × 0.40 = 1.87

Q2. Which of the following best characterize a computer that uses memory-mapped I/O?

(a) the computer provides special Instruction for manipulating the I/O port

(b) I/O ports are placed at addresses on bus and are accessed just like other memory location

(c) to perform an I/O operation, it is sufficient to place the data in an address and call the channel to perform the operation

(d) ports are reference only by memory-mapped Instruction of the computer and are located hard-wired memory location

Answer: Option (b)

Explanation: I/O ports are placed at addresses on bus and are accessed just like other memory location in computers that uses memory-mapped I/O.

Q3. Suppose, after analyzing a new cache design, you discover that the cache has far too many conflict misses, and this needs to be resolved. You know that you must increase associativity in order to decrease the number of cache misses. What are the implications of increasing associativity?

(a) Slower cache access time (b) Increase index bits

(c) Increase block size (d) All of these

Answer: Option (a)

Explanation: Increase in the associativity leads to an increase in the number of tag comparisons. Hence it leads to an increase in cache access time.

Q4. Consider the main memory of size 1024 words of 8 bits each (1K × 8). What is the number of 2 × 4 decoders with enabling line needed to construct a 16K × 16 RAM from 1K × 8 RAM              ( GATE 2013)

A.4

B.5

C.6

D.7

Answer: B (5) 

Size of Given Memory = 1K *8 = 2 13

Size of Memory to be construct = 16 K * 16 = 2 18

Number of 2 *4 Decoder required to construct 16K * 16 RAM using 1K * 8 memory = 2 18 divide by 2 13 it means 5

Q5. Identify the false statements:

S1: Separate I/O address space does not necessarily mean that I/O address lines are physically separated.

S2: Address decoder is an essential part of the I/O interface.

(a) Only S1 (b) Only S2

(c) Both S1 and S2 (d) Neither S1 nor S2

Answer: Option (d)

Explanation:

S1: Separate I/O address space does not necessarily mean that I/O address lines are physically separated from the memory address lines. A special signal on the bus indicates that the requested read or write transfer is an I/O operation.

S2: The address decoder, the data and status register, and control circuitry required to coordinate I/O transfers constitute the interface circuit (Hence true).

Q6. DMA interface unit eliminates the need to use CPU registers to transfers data from

(a) MAR to MBR (b) MBR to MAR

(c) I/O units to memory (d) Memory to I/O units

Answer: Option (d)

DMA interface unit eliminates the need to use CPU registers to transfer data from Memory I/O units.

Q7. Compared to RISC processors, CISC processors contain _________.

(a) More registers and smaller instruction set

(b) Larger instruction set and fewer registers

(c) Fewer registers and smaller instruction set

(d) More transistor elements

Answer: Option (b)

Explanation: CISC processor contains fewer registers and a larger instruction set.

Q8. For the given Sequence of micro-operations. ( GATE 2013)

MBR ← PC

MAR ← X

PC ← Y

Memory ← MBR

Which among the following is a possible operation performed by this Sequence?

A.Instruction fetch

B.Operand fetch

C.Conditional branch

D.Initiation of Interrupt

Answer: D Initiation of Interrupt

Explanation: Given Sequence of micro-operation doing the following task

1. First, micro-operation stores the value of the program counter in the memory buffer register.
2. The second micro-operation stores the value of X in the memory address register.
3. The third micro-operation stores the value of Y in the program counter.
4. The fourth micro-operation stores the value of MBR into memory.

Here we are saving the value of the PC to memory and then load the PC with the new value. This can be done in operations in case of a conditional branch and in case of interrupt service. Since here we are not checking any condition so this represents to Initiation of Interrupt Service.

Q9. Which of the following miss is definite to occur in cache memory?

(a) Cold-start miss (b) Capacity miss

(c) Conflict miss (d) All of these

Answer: Option (a)

Explanation

• Cold start misses, also called compulsory miss, will occur when the cache is empty.
• A capacity miss occurs due to the small size of cache memory; it cannot hold all the blocks required for program execution.
•  Conflict miss occurs when too many blocks are mapped into the same line or set.

Q10. Which of the following are not considered as part of the I/O interface which connects bus and I/O device?

(i) Address decoder

(ii) Control circuitry

(iii) Data and status register

(a) Only (i) and (iii) (b) Only (ii) and (iii)

(c) (i), (ii) and (iii) (d) None of these

Answer: Option (d)

Explanation:

(i) The address decoder enables the device to recognize its address when the address appears on the address lines.

(ii) Control circuitry is required to coordinate I/O transfers.

(iii) The data register holds the data being transferred to or from the processor. The status register contains information relevant to the operation of the I/O device

Q11. A two-way set-associative cache has lines of 16 bytes and a total cache size of 8 K bytes. The 256 M byte main memory is Byte addressable. Which one of the following main memory blocks are mapped onto the set ‘0’ of the cache memory?

(a) (CFED09B)16 (b) (FCED90C)16

(c) (CFED00B)16 (d) (FECD10C)16

Answer: Option (c)

Explanation:

Number of lines = 8 K16⇒29

Number of sets = 292⇒28

Physical address size = 28 bits

Two way set-associative cache.

Q12. Register renaming is done in pipeline processors ( GATE 2012)

A.as an alternative to registering allocation at compile time

B. For efficient access to function parameters and local variables

C.to handle certain kinds of hazards

D.as part of address translation

Answer: C

Register renaming is done in pipeline processors to handle certain kinds of hazards

Q13. The amount of ROM needed to implement a 4-bit multiplier is ( GATE 2012)

A.64 bits

B.128 bits

C.1 K bits

D.2 K bits

Answer: 2 K bits

Q14. Consider the following statements:

1. Time taken for a single instruction on a pipelined CPU is less than or equal to the time taken on a non-pipe lined (identical) CPU.
2. In a uniform delay pipeline, the execution time for a single instruction is equal to the execution time in the non-pipelined processor. (Assume no buffer delay)

Which of the above statement(s) is correct?

(a) Only 1 (b) Only 2

(c) Both 1 and 2 (d) Neither 1 nor 2

Answer: Option (b)

Explanation:

1. For a single instruction, the time taken on pipeline CPU is always greater than or equal to the non-pipeline.
2. When all stages have the same delay and buffer latency is zero, then for a single instruction execution time of pipeline CPU is equal to the execution time of non-pipelined CPU

Q15. Suppose the cache memory is 100 times faster than main memory, and it is used 50% of the time. The performance is gained by introducing this cache is __________.

Answer: 1.98

Apply Amdhal’s law

S = 100

f = 50% Soverall=[1−0.5+0.5/100]−1

=[0.5+0.5/100]−1=[101/200]−1=200101=1.98

Q16. Consider a 16-bit processor in which the following one address instruction is loaded in main memory.

The effective address using PC relative addressing mode when the processor is executing an instruction at location 300 is _________.

Solution: 802

Explanation:

802

EA ← PC + 500

EA ← 302 + 500

EA ← 802

Q17. The number of micro-operations required to fetch an instruction from memory is __________.

Solution: 4

Explanation:

Fetch Cycle:

T1: PC → MAR PCout, MARin

T2: M[MAR] → MBR MARout, MBRin

T3: MBR → IR MBRout, IRin

T4: PC → PC PC out, PCin

Q18. The minimum size of the ROM, which maintains a truth table of the square of 3-bit numbers, is __________ (in bits).

Solution: 48

Explanation:

Square of largest 3-bit number (111) occupies 6 bits only. Thus 6 bits are sufficient to store squares of any 3-bit number in ROM.

Square of largest 3-bit number = 49, which needs a minimum of 6 bits.

∴ 8 × 6 = 48 bits

Q19. Consider a cache with 64 blocks and a block size of 16 bits. The block number of byte address 1600 is __________.

Solution: 36

Explanation:1600/Block size=1600/16=100

100th block in main memory.

∴ Location in cache = 100 mod 64 = 36th block in cache.

Q20. Consider a 5 stage pipeline with IF, ID, EX, MEM, and WB latencies 8, 6, 4, 6, and 4, respectively (in ns). If IF stage is made 50% faster, the percentage it will improve the performance CPU is __________.

Answer: 14.3 (14-15)

In non-pipeline total latency (without enhance)

= 8 + 6 + 4 + 6 + 4 = 28

with improvement = 4 + 6 + 4 + 6 + 4 = 24

% improvement = (28−24)/28=428=14.3%

Q21. A computer has a cache memory of size 256 Kbyte, and it is a 4-way set associated with a block size of 32 Bytes. The processor sends 32-bit addresses to the cache controller. Each cache tag directory entry contains, in addition, to address tag, two valid bits, one modified bit, and 1 replacement bit. (GATE 2012)

The number of bits in the tag field of an address is

(A) 11

(B) 14

(C) 16

(D) 27

Answer: (C)

Cache memory size is 256 KB = 256 * 1024 Byte

Cache Block size is 32 byte = 32 Byte

SO Total number of Blocks in cache memory= ( 256 * 1024) / 32 = 8192

Since cache memory is a four-way set-associative so, One set consists of 4 blocks.

So total Sets in Cache Memory = 8192 / 4 = 2048

And 2048 = 211

So 11 Bits are required for the SET Field of the address.

The total bits in address is 32. It consists of three fields BYTE, SET, and TAG.

The size of one Block is 32 byte = 25. Byte SO 5 Bits are required to represent the Byte Filed. 11 Bits are required for SET filed, so the Remaining ( 32- ( 11+5) ) = 16 Bits are used for the TAG field.

Q22. A certain architecture supports indirect, direct, and register addressing modes for use in identifying operands for arithmetic instructions. Which of the following cannot be achieved with a single instruction?

(a) specifying a register number in the Instruction such that the register contains the value of an operand that will be used by the operation.

(b) specifying a register number in the Instruction such that the register will serve as the

destination for the operation’s output.

(c) specifying an operand value in the Instruction such that the value will be used by the

operation.

(d) specifying a memory location in the Instruction such that the memory location contains the value of an operand that will be used by the operation.